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1 ltc1588/ltc1589/ltc1592 1588992fa n six programmable output ranges unipolar mode: 0v to 5v, 0v to 10v bipolar mode: 5v, 10v, 2.5v, C 2.5v to 7.5v n 1lsb max dnl and inl over the industrial temperature range n glitch impulse < 2nv-s n 16-lead ssop package n power-on reset to 0v n asynchronous clear to 0v for all ranges the ltc ? 1588/ltc1589/ltc1592 are serial input 12-/14- /16-bit multiplying current output dacs that operates from a single 5v supply. these softspan tm dacs can be software-programmed for either unipolar or bipolar mode through a 3-wire spi interface. in either mode, the voltage output range can also be software-programmed. two output ranges in unipolar mode and four output ranges in bipolar mode are available. inl and dnl are accurate to 1lsb over the industrial temperature range in both unipolar and bipolar modes. true 16-bit 4-quadrant multiplication is achieved with on-chip four quadrant multiplication resistors. the ltc1588/ltc1589/ltc1592 are available in a 16-lead ssop package. these devices include an internal deglitcher circuit that reduces the glitch impulse to less than 2nv-s (typ). the asynchronous clear pin resets the ltc1588/ltc1589/ ltc1592 to 0v in unipolar or bipolar mode. n process control and industrial automation n precision instrumentation n direct digital waveform generation n software-controlled gain adjustment n automatic test equipment 12-/14-/16-bit softspan dacs with programmable output range + 1/2 lt 1469 + 1/2 lt1469 16-bit dac with span adjust ltc1592 r com 1 r1 2 v cc 0.1 f 9 r2 r2 r1 16 r ofs 3 7 5 v ref 5v 6 ref 15 r fb i out1 v out 4 5v 5 1 2 3 i out2 agnd gnd clr cs/ld sck sdi sdo 6 7 8 14 13 12 11 10 c2 150pf c1 15pf 1588992 ta01 15v 15v 8 4 0.1 f 0.1 f , ltc and lt are registered trademarks of linear technology corporation. programmable output range 16-bit softspan dac digital input code 0 integral nonlinearity (lsb) 1.0 0.8 0.6 0.4 0.2 0 0.2 0.4 0.6 0.8 1.0 16384 32768 1588992 ta02 49152 65535 v ref = 5v all output ranges ltc1592 integral nonlinearity softspan is a trademark of linear technology corporation. features descriptio u applicatio s u typical applicatio u
2 ltc1588/ltc1589/ltc1592 1588992fa t jmax = 150 c, q ja = 125 c/ w order part number (note 1) v cc to agnd, gnd ......................................C 0.3v to 7v agnd to gnd .............................. C 0.3v to (v cc + 0.3v) gnd to agnd .............................. C 0.3v to (v cc + 0.3v) r com to agnd, gnd ................................ C 0.3v to 12v ref to agnd, gnd ................................................ 15v r ofs , r fb , r1, r2 to agnd, gnd .......................... 15v digital inputs to agnd, gnd ....... C 0.3v to (v cc + 0.3v) i out1 , i out2 to agnd, gnd .......... C 0.3v to (v cc + 0.3v) maximum junction temperature .......................... 150 c operating temperature range ltc1588c/ltc1589c/ltc1592c ........... 0 c to 70 c ltc1588i/ltc1589i/ltc1592i ........... C 40 c to 85 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c ltc1588cg ltc1588ig ltc1589cg LTC1589IG ltc1592acg ltc1592aig ltc1592bcg ltc1592big the l denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = t min to t max , v cc = 5v, v ref = 5v, i out2 = agnd = gnd = 0v. consult ltc marketing for parts specified with wider operating temperature ranges. electrical characteristics 1 2 3 4 5 6 7 8 top view g package 16-lead plastic ssop 16 15 14 13 12 11 10 9 r2 ref clr cs/ld sck sdi sdo v cc r com r1 r ofs r fb i out1 i out2 agnd gnd package/order i for atio uu w absolute axi u rati gs w ww u ltc1588 ltc1589 ltc1592b ltc1592a symbol parameter conditions temperature min typ max min typ max min typ max min typ max units accuracy resolution l 12 14 16 16 bits inl integral (notes 2, 3) t a = 25 c 1 1 2 0.3 1lsb nonlinearity t min to t max l 1 1 2 0.4 1lsb dnl differential guaranteed t min to t max l 1 1 1 0.2 1lsb nonlinearity monotonic (note 3) ge gain error all output ranges t a = 25 c C0.20 3 C1.0 4C3 16 C2 16 lsb (note 3) t min to t max l C0.22 3 C1.3 6C4 24 C3 16 lsb bze bipolar zero error all bipolar ranges t a = 25 c 1 2.5 10 5lsb (note 3) t min to t max l 1 4.0 16 8lsb gain temperature d gain/ d temperature l 3 3 3 1 3 ppm/ c coefficient (note 4) i lkg i out1 leakage (note 5) t a = 25 c 5 5 5 5na current t min to t max l 15 15 15 15 na psrr power supply v cc = 5v 10% l 0.01 0.15 0.05 0.5 2 0.2 2 lsb/v rejection
3 ltc1588/ltc1589/ltc1592 1588992fa electrical characteristics the l denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = t min to t max , v cc = 5v, v ref = 5v, i out2 = agnd = gnd = 0v. symbol parameter conditions min typ max units reference input r ref dac input resistance (unipolar) (note 6) l 5710 k w r1, r2 r1, r2 resistance (notes 6, 11) l 10 14 20 k w r ofs offset resistance (bipolar) 5v, 10v, 2.5v ranges l 10 14 20 k w C2.5v to 7.5v range l 20 28 40 k w r fb feedback resistance (unipolar) 5v range l 5710 k w 10v range l 10 14 20 k w feedback resistance (bipolar) 5v and C2.5v to 7.5v ranges l 10 14 20 k w 10v range l 20 28 40 k w 2.5v range l 5710 k w analog outputs (note 4) c out output capacitance (i out1 ) dac load all 1s 160 pf dac load all 0s 100 pf ac performance (note 4) settling time 5v range, 0v to 5v step with lt1468 (note 7) 2 m s midscale glitch impulse (note 10) 2 nv-s multiplying feedthrough error v ref = 10v, 10khz sine wave 1 mv p-p thd total harmonic distortion (note 8) multiplying C 108 db output noise voltage density (note 9) at i out1 11 nv/ ? hz digital inputs v ih digital input high voltage l 2.4 v v il digital input low voltage l 0.8 v i in digital input current l 1 m a c in digital input capacitance v in = 0v (note 4) l 8pf digital outputs v oh digital output high voltage i oh = 200 m a l 4v v ol digital output low voltage i ol = 1.6ma l 0.4 v timing characteristics t 1 serial input valid to sck setup time l 60 ns t 2 serial input valid to sck hold time l 0ns t 3 sck pulse width high l 35 ns t 4 sck pulse width low l 35 ns t 5 cs/ld pulse high width l 360 ns t 6 lsb sck high to cs/ld high l 35 ns t 7 cs/ld low to sck high l 0ns t 8 sck to sdo propagation delay c load = 50pf l 20 180 ns t 9 sck low to cs/ld low l 35 ns t 10 clear pulse low width l 100 ns t 11 cs/ld high to sck positive edge l 35 ns sck frequency non-daisy chain (note 12) l 14.2 mhz daisy chain (note 13) 4.1 mhz
4 ltc1588/ltc1589/ltc1592 1588992fa note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: 1lsb = 0.0015% of full scale = 15.3ppm of full scale (ltc1592). 1lsb = 0.006% of full scale = 61.2ppm of full scale (ltc1589). 1lsb = 0.024% of full scale = 244.8ppm of full scale (ltc1588). note 3: using internal feedback resistor. note 4: guaranteed by design, not subject to test. note 5: i out1 with dac register loaded to all 0s. note 6: typical temperature coefficient is 100ppm/ c. note 7: to 0.0015% for a full-scale change, measured from the falling edge of ld for the ltc1592 only. note 8 : ref = 6v rms at 1khz. dac register loaded with all 1s. output amplifier = lt1468. electrical characteristics the l denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = t min to t max , v cc = 5v, v ref = 5v, i out2 = agnd = gnd = 0v. symbol parameter conditions min typ max units power supply v cc supply voltage l 4.5 5 5.5 v i cc supply current, v cc digital inputs = 0v or v cc l 10 m a note 9: calculation from e n = ? 4ktrb where: k = boltzmann constant (1.38e-23 j/ k); r = resistance ( w ); t = temperature ( k); b = bandwidth (hz). note 10: midscale transition code: 32767 to 32768 for the ltc1592, 8191 to 8192 for the ltc1589, 2047 to 2048 for the ltc1588. note 11: r1 and r2 are measured between r1 and r com , r2 and r com . note 12: if a continuous clock is used with data changing on the rising edge of sck, setup and hold time (t 1 , t 2 ) will limit the maximum clock frequency. if data changes on the falling edge of sck then the setup time will limit the maximum clock frequency to 8mhz (continuous 50% duty cycle clock). note 13: sdo propagation delay and sdi setup time (t 8 , t 1 ) limit the maximum clock frequency for daisy chaining. typical perfor a ce characteristics uw time ( s) 0 output voltage (mv) ?0 0 10 0.6 1.0 1588992 g03 ?0 ?0 ?0 0.2 0.4 0.8 20 30 40 using an lt1468 c feedback = 30pf v ref = 10v 1nv-s typical midscale glitch impulse (ltc1588/ltc1589/ltc1592) supply current vs input voltage input voltage (v) 0 supply current (ma) 3 4 5 4 1588992 g09 2 1 0 1 2 3 5 v cc = 5v all digital inputs tied together logic threshold vs supply voltage supply voltage (v) 0 0 logic threshold (v) 0.5 1.0 1.5 2.0 3.0 1 234 1588992 g10 57 6 2.5
5 ltc1588/ltc1589/ltc1592 1588992fa typical perfor a ce characteristics uw (ltc1588) integral nonlinearity differential nonlinearity digital input code 0 integral nonlinearity (lsb) 0.2 0.6 1.0 1588992 g11 0.2 0.6 0 0.4 0.8 0.4 0.8 ?.0 800 1600 2400 3200 4095 digital input code 0 differential nonlinearity (lsb) 0.2 0.6 1.0 1588992 g12 0.2 0.6 0 0.4 0.8 0.4 0.8 ?.0 800 1600 2400 3200 4095 (ltc1589) integral nonlinearity differential nonlinearity digital input code 0 integral nonlinearity (lsb) 0.2 0.6 1.0 1588992 g13 0.2 0.6 0 0.4 0.8 0.4 0.8 ?.0 4112 8224 12336 16383 digital input code 0 differential nonlinearity (lsb) 0.2 0.6 1.0 1588992 g14 0.2 0.6 0 0.4 0.8 0.4 0.8 ?.0 4112 8224 12336 16383 integral nonlinearity vs reference voltage in unipolar mode reference voltage (v) ?0 integral nonlinearity (lsb) 0.2 0.6 1.0 6 1588992 g05 0.2 0.6 0 0.4 0.8 0.4 0.8 1.0 ? ? 2 ? 8 ? 0 4 10 integral nonlinearity (inl) digital input code 0 1.0 integral nonlinearity (lsb) 0.8 0.4 0.2 0 1.0 0.4 16384 32768 1588992 g01 0.6 0.6 0.8 0.2 49152 65535 digital input code 0 1.0 differential nonlinearity (lsb) 0.8 0.4 0.2 0 1.0 0.4 16384 32768 1588992 g02 0.6 0.6 0.8 0.2 49152 65535 differential nonlinearity (dnl) (ltc1592)
6 ltc1588/ltc1589/ltc1592 1588992fa reference voltage (v) ?0 integral nonlinearity (lsb) 0.2 0.6 1.0 6 1588992 g06 0.2 0.6 0 0.4 0.8 0.4 0.8 1.0 ? ? 2 ? 8 ? 0 4 10 integral nonlinearity vs reference voltage in bipolar mode differential nonlinearity vs reference voltage in unipolar mode reference voltage (v) ?0 differential nonlinearity (lsb) 0.2 0.6 1.0 6 1588992 g07 0.2 0.6 0 0.4 0.8 0.4 0.8 1.0 ? ? 2 ? 8 ? 0 4 10 typical perfor a ce characteristics uw differential nonlinearity vs reference voltage in bipolar mode reference voltage (v) ?0 differential nonlinearity (lsb) 0.2 0.6 1.0 6 1588992 g08 0.2 0.6 0 0.4 0.8 0.4 0.8 1.0 ? ? 2 ? 8 ? 0 4 10 (ltc1592) uu u pi fu ctio s r com (pin 1): center tap point of the two bipolar resis- tors r1 and r2. normally tied to the inverting input of an external amplifier. when these resistors are not used, connect this pin to ground. the absolute maximum volt- age range on this pin is C 0.3v to 12v. r1 (pin 2): bipolar resistor r1. the main reference input v ref , typically 5v. accepts up to 15v. normally tied to r ofs (pin 3) and the reference input voltage v ref (5v). when not used connect this pin to ground. r ofs (pin 3): bipolar offset network. this pin provides the offset of the output voltage range for bipolar modes. accepts up to 15v. normally tied to r1 and the reference input voltage v ref (5v). alternatively, this pin may be driven from a different voltage than v ref . r fb (pin 4): feedback network. normally tied to the output of the current to voltage converter op amp. range limited to 15v. full-scale settling waveform gated settling waveform 500 m v/div ld pulse 5v/div 500ns/div 1592 g04 using lt1468 op amp c feedback = 20pf 0v to 10v step
7 ltc1588/ltc1589/ltc1592 1588992fa i out1 (pin 5): true dac current output. tied to the inverting input of the current-to-voltage op amp. i out2 (pin 6): complement of dac current output. nor- mally tied to agnd pin. agnd (pin 7): analog ground. tie to the systems analog ground plane. gnd (pin 8): ground. tie to the systems analog ground plane. v cc (pin 9): positive supply input. 4.5v v cc 3 5.5v. requires a 0.1 m f bypass capacitor to ground. sdo (pin 10): serial data output. data at this pin is shifted out on the rising edge of sck. sdi (pin 11): serial data input. uu u pi fu ctio s fu ctio table u u table 1 c3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 c2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 c1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 c0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 sreg data word dn in input shift register dn x dn dn dn dn dn dn dn x buf1 input buffer dn dn dn dn dn dn dn dn dn no change dac output range no change no change no change 5v 10v 5v 10v 2.5v ?.5v to 7.5v no change buf2 dac buffer (dac output) no change dn dn dn dn dn dn dn dn no change copy data word dn in sreg to buf1 copy the data in buf1 to buf2 copy data word dn in sreg to buf1 and buf2 reserved (do not use) reserved (do not use) reserved (do not use) reserved (do not use) reserved (do not use) set range to 5v. copy dn in sreg to buf1 and buf2 set range to 10v. copy dn in sreg to buf1 and buf2 set range to 5v. copy dn in sreg to buf1 and buf2 set range to 10v. copy dn in sreg to buf1 and buf2 set range to 2.5v. copy dn in sreg to buf1 and buf2 set range to ?.5v to 7v. copy dn in sreg to buf1 and buf2 reserved (do not use) no operation internal register status operation each command is executed on the rising edge of cs/ld command data word dn (n = 0 to 15) is the last 16 bits shifted into the input shift register sreg that corresponds to the dac code. sck (pin 12): serial interface clock. data on the sdi pin is shifted into the input shift register on rising edge of sck. cs/ld (pin 13): chip select input. when cs/ld is low, sck is enabled for shifting data into the input shift register. when cs/ld is pulled high, sck is disabled and the control logic executes the control word (the first 4 bits of the input data stream as shown in table 1). clr (pin 14): when clr is taken to a logic low, it sets the dac output to 0v and all internal registers to zero code. ref (pin 15): dac reference input. typically 5v, accepts up to 15v. r2 (pin 16): bipolar resistor r2. normally tied to the dac reference input ref (pin 15) and the output of the inverting amplifier tied to r com (pin 1).
8 ltc1588/ltc1589/ltc1592 1588992fa block diagra w 12-/14-/16-bit dac 12/14/16 bits 1588992 bd buffer 12/14/16 bits 12-/14-/16-bit data word dn 4 bit command word buffer decoder 24-bit shift register sreg 8-bit shift register sdo sck sdi cs/ld buf2 buf1 span adjust sdi sdo cs/ld sck 1588992 td t 2 t 8 t 9 t 11 t 5 t 7 1 2 23 24 t 6 t 1 t 3 t 4 ti i g diagra u ww
9 ltc1588/ltc1589/ltc1592 1588992fa operatio u serial interface when the cs/ld is brought to a logic low, the data on the sdi input is loaded into the shift register on the rising edge of the clock. a 4-bit command word (c3 c2 c1 c0), followed by four dont care bits and 16 data bits (msb-first) is the minimum loading sequence required for the ltc1588/ltc1589/ltc1592. when the cs/ld is brought to a logic high, the clock is disabled internally and the command word is executed. if no daisy-chaining is required, the input stream can be 24-bit wide as shown in figure 1a. the first four bits are the command word, followed by four dont care bits, then a 16-bit data word. the last four bits (lsbs) of this 16-bit data word are dont cares for the ltc1588. for the ltc1589, the last 2 bits of the 16-bit data word are dont cares. if daisy-chaining is required or the input needs to be written in two 16-bit wide segments, then the input stream must be 32-bit wide and the first 8 bits loaded are dont care bits. the remaining bits work the same as a 24-bit stream which is described in the previous paragraph. the output of the internal 32-bit shift register is available on the sdo pin 32 clock cycles later. multiple ltc1588/ltc1589/ltc1592s may be daisy- chained together by connecting the sdo pin to the sdi pin of the next ic. the clock and cs/ld signals should remain common to all ics in the daisy-chain. the serial data is clocked to all ics, then the cs/ld signal is pulled high to update all of them simultaneously. power-on reset and clear when the power supply is first turned on, the ltc1588/ ltc1589/ltc1592 will power up in 5v unipolar mode (c3 c2 c1 c0 = 1000). all the internal registers are set to zeros and the dac is set to zero code. the ltc1588/ltc1589/ltc1592 must first be pro- grammed in either unipolar or bipolar mode. there are six operating modes available and can be software-pro- grammed by the command word. when a clr signal is brought to low, it clears all internal registers to zero. the dac output voltage goes to zero volts. if an update dac command (c3 c2 c1 c0 = 0001) is issued immediately after the clr signal, the dac output remains at zero volts. if a clr signal is given within a 100ns interval immediately after cs/ld goes high, the user should reload the output range. output range programming there are two output ranges available in unipolar mode and four output ranges available in bipolar mode. see function table for details. all output ranges are with re- spect to a 5v reference input. when changing the ltc1588/ ltc1589/ltc1592 to a new mode, the command word and data are given at the same time (24 or 32 bit). when c3 command don? care data (16 bits) c2 c1 c0 x x x x d13 d14 d15 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1588992 td2 msb lsb c3 command don? care data (14 bits + 2 don?-care bits) c2 c1 c0 x x x x d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x 1588992 td3 msb lsb c3 command don? care data (12 bits + 4 don?-care bits) c2 c1 c0 x x x x d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x xx 1588992 td4 msb lsb input word (ltc1592) input word (ltc1589) input word (ltc1588)
10 ltc1588/ltc1589/ltc1592 1588992fa figure 1a. ltc1592 24-bit load sequence (minimum input word) ltc1589 sdi data word = 14-bit input code + 2 dont care bits at lsb positions ltc1588 sdi data word = 12-bit input code + 4 dont care bits at lsb positions operatio u 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 c2 c1 c0 x x x x d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 c3 cs/ld sck sdi control word don? care (reserved) data word dn 24-bit data stream (cannot be daisy-chained) 1588992 f01a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 c2 c1 c0 x x x x d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 c3 x x x x x x x x cs/ld sck sdi control word don? care data word dn 32-bit data stream (can be daisy-chained) don? care c2 c1 c0 x x x x d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 c3 x x x x x x x x sdo current 32-bit input word 1588992 f01b previous 32-bit input word t 2 t 3 t 4 t 1 t 8 d15 17 sck sdi sdo previous d14 previous d15 18 d14 figure 1b. ltc1592 32-bit load sequence (required for daisy-chain operation) ltc1589 sdi/sdo data word = 14-bit input code + 2 dont care bits at lsb positions ltc1588 sdi/sdo data word = 12-bit input code + 4 dont care bits at lsb positions
11 ltc1588/ltc1589/ltc1592 1588992fa applicatio s i for atio wu uu op amp selection because of the extremely high accuracy of the 16-bit ltc1592, careful thought should be given to op amp selection in order to achieve the exceptional performance of which the part is capable. fortunately, the sensitivity of inl and dnl to op amp offset has been greatly reduced compared to previous generations of multiplying dacs. tables 2 and 3 contain equations for evaluating the effects of op amp parameters on the ltc1592s accuracy when programmed in a unipolar or bipolar output range. these are the changes the op amp can cause to the inl, dnl, unipolar offset, unipolar gain error, bipolar zero and bipo- lar gain error. tables 2 and 3 can also be used to determine the effects of op amp parameters on the ltc1589 and the ltc1588. however, the results obtained from tables 2 and 3 are in 16-bit lsbs. divide these results by 4 (ltc1589) and 16 (ltc1588) to obtain the correct lsb sizing. table 4 contains a partial list of ltc precision op amps recommended for use with the ltc1592. the easy-to-use design equations simplify the selection of op amps to meet the systems specified error budget. select the amplifier from table 4 and insert the specified op amp parameters in table 3. add up all the errors for each category to determine the effect the op amp has on the accuracy of the ltc1592. arithmetic summation gives an (unlikely) worst- case effect. a root-sum-square (rms) summation pro- duces a more realistic estimate. op amp offset will contribute mostly to output offset and gain error and has minimal effect on inl and dnl. for the ltc1592, a 250 m v op amp offset will cause about 0.65lsb inl degradation and 0.15lsb dnl degradation with a 10v full-scale range (20v range in bipolar). for the ltc1592 programmed in a unipolar mode, the same 250 m v op amp offset will cause a 3.3lsb zero-scale error and a 3.3lsb gain error with a 10v full-scale range. cs/ld goes high, the mode changes and the dac output goes to a value corresponding to the data code. examples using the ltc1592: 1. using a 24-bit loading sequence, load the unipolar range of 0v to 10v with the dac output at zero volt: a) cs/ld b) clock sdi = 1001 xxxx 0000 0000 0000 0000 c) cs/ld ; then v out = 0v 2. using a 24-bit loading sequence, load the bipolar range of 5v and the dac output at zero volt: a) cs/ld b) clock sdi = 1010 xxxx 1000 0000 0000 0000 c) cs/ld ; then v out = 0v on the 5v range 3. using a 32-bit load sequence, load the bipolar range of 10v with the dac output voltage at 5v initially. then change the dac output to C5v: a) cs/ld b) clock sdi = xxxx xxxx 1011 xxxx 1100 0000 0000 0000 c) cs/ld ; then v out = 5v on the 10v range next, the bipolar range of 10v is retained and the dac output voltage is changed to v out = C 5v: a) cs/ld b) clock sdi = xxxx xxxx 0010 xxxx 0100 0000 0000 0000 c) cs/ld ; then v out = C 5v on the 10v range operatio u
12 ltc1588/ltc1589/ltc1592 1588992fa while not directly addressed by the simple equations in tables 2 and 3, temperature effects can be handled just as easily for unipolar and bipolar applications. first, consult an op amps data sheet to find the worst-case v os and i b over temperature. then, plug these numbers in the v os and i b equations from table 3 and calculate the tempera- ture induced effects. for applications where fast settling time is important, appli- cation note 74, entitled component and measurement advances ensure 16-bit dac settling time , offers a thor- ough discussion of 16-bit dac settling time and op amp selection. precision voltage reference considerations much in the same way selecting an operational amplifier for use with the ltc1592 is critical to the performance of the system, selecting a precision voltage reference also requires due diligence. the output voltage of the ltc1592 is directly affected by the voltage reference; thus, any voltage reference error will appear as a dac output voltage error. there are three primary error sources to consider when selecting a precision voltage reference for 16-bit applica- tions: output voltage initial tolerance, output voltage tem- perature coefficient and output voltage noise. initial reference output voltage tolerance, if uncorrected, generates a full-scale error term. choosing a reference applicatio s i for atio wu uu table 4. partial list of ltc precision amplifiers recommended for use with the ltc1588/ltc1589/ltc1592, with relevant specifications amplifier specifications voltage current slew gain bandwidth t settling power v os i b a ol noise noise rate product with ltc1592 dissipation amplifier m v na v/mv nv/ ? hz pa/ ? hz v/ m s mhz m smw lt1001 25 2 800 10 0.12 0.25 0.8 120 46 lt1097 50 0.35 1000 14 0.008 0.2 0.7 120 11 lt1112 (dual) 60 0.25 1500 14 0.008 0.16 0.75 115 10.5/op amp lt1124 (dual) 70 20 4000 2.7 0.3 4.5 12.5 19 69/op amp lt1468 75 10 5000 5 0.6 22 90 2.5 117 lt1469 (dual) 125 10 2000 5 0.6 22 90 2.5 123/op amp () 5v v ref () 5v v ref () 16.5k a vol1 op amp v os1 (mv) i b1 (na) a vol1 (v/v) v os2 (mv) i b2 (mv) a vol2 (v/v) v os1 ?2.4 ? i b1 ?0.0003 a1 ? 0 0 0 inl (lsb) () 5v v ref () 5v v ref () 1.5k a vol1 () 66k a vol2 () 131k a vol1 () 131k a vol1 () 131k a vol2 () 131k a vol2 v os1 ?0.6 ? i b1 ?0.00008 a2 ? 0 0 0 dnl (lsb) () 5v v ref () 5v v ref v os1 ?13.2 ? i b1 ?0.13 0 0 0 0 unipolar offset (lsb) () 5v v ref () 5v v ref () 5v v ref v os1 ?13.2 ? i b1 ?0.0018 ? a5 ? v os2 ?26.2 i b2 ?0.1 bipolar gain error (lsb) () 5v v ref () 5v v ref () () () 5v v ref () 5v v ref a3 ?v os1 ?19.8 ? i b1 ?0.01 0 a4 ? v os2 ?13.1 a4 ? i b2 ?0.05 a4 ? bipolar zero error (lsb) unipolar gain error (lsb) () 5v v ref () 5v v ref () 5v v ref () 5v v ref () 5v v ref v os1 ?13.2 ? i b1 ?0.0018 ? a5 v os2 ?26.2 i b2 ?0.1 table 3. easy-to-use equations determine op amp effects on dac accuracy in all output ranges table 2. variables for each output range that adjust the equations in table 3 output range a1 a2 a3 a4 a5 5v 1.1 2 1 10v 2.2 3 1.5 5v 2 2 1.2 1 1.5 10v 4 4 1.2 1 2.5 2.5v 1 1 1.6 1 1 C2.5v to 7.5v 1.9 3 1 0.5 1.5
13 ltc1588/ltc1589/ltc1592 1588992fa applicatio s i for atio wu uu with low output voltage initial tolerance, like the lt1236 ( 0.05%), minimizes the gain error caused by the refer- ence; however, a calibration sequence that corrects for system zero- and full-scale error is always recommended. a references output voltage temperature coefficient af- fects not only the full-scale error, but can also affect the circuits inl and dnl performance. if a reference is chosen with a loose output voltage temperature coeffi- cient, then the dac output voltage along its transfer characteristic will be very dependent on ambient condi- tions. minimizing the error due to reference temperature coefficient can be achieved by choosing a precision reference with a low output voltage temperature coeffi- cient and/or tightly controlling the ambient temperature of the circuit to minimize temperature gradients. as precision dac applications move to 16-bit and higher performance, reference output voltage noise may contrib- ute a dominant share of the systems noise floor. this in turn can degrade system dynamic range and signal-to- noise ratio. care should be exercised in selecting a voltage reference with as low an output noise voltage as practical for the system resolution desired. precision voltage refer- ences, like the lt1236, produce low output noise in the 0.1hz to 10hz region, well below the 16-bit lsb level in 5v or 10v full-scale systems. however, as the circuit band- widths increase, filtering the output of the reference may be required to minimize output noise. table 5. partial list of ltc precision references recommended for use with the ltc1588/ltc1589/ltc1592 with relevant specifications initial temperature 0.1hz to 10hz reference tolerance drift noise lt1019a-5, 0.05% 5ppm/ c12 m v p-p lt1019a-10 lt1236a-5, 0.05% 5ppm/ c3 m v p-p lt1236a-10 lt1460a-5, 0.075% 10ppm/ c20 m v p-p lt1460a-10 lt1790a-2.5 0.05% 10ppm/ c12 m v p-p grounding as with any high resolution converter, clean grounding is important. a low impedance analog ground plane and star grounding techniques should be used. i out2 must be tied to the star ground with as low a resistance as possible. when it is not possible to locate star ground close to i out2 , a low resistance trace should be used to route this pin to star ground. this minimizes the voltage drop from this pin to ground caused by the code dependent current flowing to ground. when the resistance of this circuit board trace becomes greater than 1 w , a force/sense amplified con- figuration should be used to drive this pin (see figure 2). this preserves the excellent accuracy (1lsb inl and dnl) of the ltc1588/ltc1589/ltc1592. an isolated 16-bit subsystem using the ltc1592 the circuit in figure 4 is a complete example of an optically isolated analog output subsystem that supports most of the legacy ranges that are still common in industrial environments. this circuit uses only two optoisolators, the load pulse (cs/ld) being derived from a series of transitions on the data line (sdi) after the clock (sck) is halted high. if a single chip microcontroller with an auto- mated spi interface is to be used, the spi port can transfer the 24 bits as three bytes. subsequently, the data output port pin can be reassigned to general purpose port opera- tion and exercised to produce a number of transitions to generate the load pulse. alternatively, the entire sequence can be programmed bit by bit with a general purpose port. figure 5 shows the timing. the dc/dc converter, figure 3 based on the lt ? 3439 ultralow noise transformer driver provides a compact means of powering this circuit, and allows the output to deliver output current that is only limited by the lt1468 capabilities. the output capability of the dc/dc converter itself is 80ma at 12v and is available as demo board dc511a. this circuit as shown requires approximately 130ma of the 5v supply (no load). the total surface area required is less than 2 square inches.
14 ltc1588/ltc1589/ltc1592 1588992fa applicatio s i for atio wu uu figure 3. isolated power supplies for the circuit of figure 4 3 13 11 r1 1m r9 10k r2 16.9k r3 15k t1 ctx02-16030 d1 mmbd914 d2 mmbd914 d3 mmbd914 c3 22 f 25v cer 24 14 5 3 2 5 1 3 d4 mmbd914 c22 2.2nf 1kv e1 v in 5v 5% e5 shdn e7 sync e6 gnd c1 4.7 f 6.3v c2 820pf 5 6 7 14 4 rsl pgnd pgnd gnd colb rt 10 1 16 ct sync cola shdn v in lt3439 c7 0.01 f 2.2 f 5v c8 0.01 f c4 22 f 25v cer r10 10k r4 442k r7 442k r5 49.9k 12v agnd ?2v 1588992 f03 c5 33 f 25v tant r6 49.9k in out byp lt1761 gnd adj in out byp lt1964 gnd adj + c6 33 f 25v tant + lt1121-5 v in + 1/2 lt1469 + + 1/2 lt1469 12-/14-/16-bit dac with span adjust ltc1588/ltc1589/ltc1592 r com 1 r1 2 v cc 0.1 f 9 r2 r2 r1 16 r ofs 3 7 5 v ref 5v 6 ref 15 r fb i out1 v out 4 6 1 23 i out2 2 3 *schottky barrier diode **for multiplying applications c3 = 15pf zetex* bat54s lt1001 5v 5 1 2 3 i out2 agnd gnd clr cs/ld sck sdi sdo 6 7 8 14 13 12 11 10 c3** 150pf c2 15pf 1588992 f02 15v 15v 8 4 0.1 f 0.1 f 1000pf alternate amplifier for optimum settling time performance 6 1 23 6 + lt1468 3 zetex bat54s 2 200 200 i out2 figure 2. basic connections for softspan v out dac with two optional circuits for driving i out2 from agnd with a force/sense amplifier
15 ltc1588/ltc1589/ltc1592 1588992fa u package descriptio g package 16-lead plastic ssop (5.3mm) (reference ltc dwg # 05-08-1640) information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. g16 ssop 0802 0.09 ?0.25 (.0035 ?.010) 0 ?8 0.55 ?0.95 (.022 ?.037) 5.00 ?5.60** (.197 ?.221) 7.40 ?8.20 (.291 ?.323) 1234 5 6 7 8 5.90 ?6.50* (.232 ?.256) 14 13 12 11 10 9 15 16 2.0 (.079) 0.05 (.002) 0.65 (.0256) bsc 0.22 ?0.38 (.009 ?.015) millimeters (inches) dimensions do not include mold flash. mold flash shall not exceed .152mm (.006") per side dimensions do not include interlead flash. interlead flash shall not exceed .254mm (.010") per side * ** note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale 0.42 0.03 0.65 bsc 5.3 ?5.7 7.8 ?8.2 recommended solder pad layout 1.25 0.12
16 ltc1588/ltc1589/ltc1592 1588992fa lt/tp 0503 1k rev a ? printed in usa ? linear technology corporation 2001 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear.com part number description comments ltc1591/ltc1597 parallel 14-/16-bit current output dacs on-chip 4-quadrant resistors ltc1595/ltc1596 serial 16-bit current output dacs low glitch, 1lsb maximum inl, dnl ltc1599 2-byte, 16-bit current output dac on-chip 4-quadrant resistors ltc1821 parallel 16-bit voltage outupt dac precision 16-bit settling in 2 m s for 10v step ltc2600/ltc2610 octal 16-/14-/12-bit dacs single supply, m power in narrow ssop16 ltc2620 related parts applicatio s i for atio wu uu + lt1468 ?2v 12v + lt1468 12-/14-/16-bit dac with span adjust ltc1588/ltc1589/ltc1592 r com 1 r1 2 v cc 0.1 f 9 r2 r2 r1 16 r ofs 3 6 10 f 0.1 f 0.1 f 10 f 7 4 2 5v ref 4 2 8 12v 3 ref 15 r fb i out1 v out 4 5v 5 6 6 2 3 i out2 agnd gnd clr cs/ld sck sdi sdo 7 8 14 13 12 11 10 150pf 15pf 1588992 f04 12v 12v 7 4 0.1 f agnd agnd 0.1 f 10 f 10 f 10 f + lt1027-5 a b c d clk enp ent ld clr 14 13 12 11 3 4 5 6 2 7 10 9 1 qa qb qc qd rco gnd 5v 15 isolated sdi isolated sck optional circuit for 2-wire interface. for a 3-wire interface (spi), add a 3rd optoisolator to drive cs/ld with the waveforms of figure 1 isolated cs/ld 74hc161 5 6 2 v cc sck 3 r1 7.5k 7 8 5v hcpl2300 5 6 2 v cc sdi to controller 3 r2 7.5k 7 8 5v hcpl2300 figure 4. optically isolated 16-bit softspan system c3 c2 c1 c0 x d2 d1 d0 sck sdi cs/ld 1588992 f05 figure 5. timing diagram for the circuit of figure 4

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